LSN2A Datasheet, PDF (11/15 Pages) Murata Manufacturing Co., Ltd. – Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters

LSN2 Series
Non-isolated, DOSA-SIP, 6/10/16A
Selectable-Output DC/DC Converters
other method. Several standard sequencing architectures are prevalent. They
are concerned with three factors:
■ The time relationship between the Master and Slave voltages
■ The voltage difference relationship between the Master and Slave
■ The voltage slew rate (ramp slope) of each converter’s output.
For most systems, the time relationship is the dominant factor. The voltage
difference relationship is important for systems very concerned about possible
latchup of programmable devices or overdriving ESD diodes. Lower slew
rates avoid overcurrent shutdown during bypass cap charge-up.
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Figure 8. Coincident or Simultaneous Phasing (Identical Slew Rates)
In Figure 8, two POL’s ramp up at the same rate until they reach their dif-
ferent respective final set point voltages. During the ramp, their voltages are
nearly identical. This avoids problems with large currents flowing between
logic systems which are not initialized yet. Since both end voltages are differ-
ent, each converter reaches it’s setpoint voltage at a different time.
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Figure 9. Proportional or Ratiometric Phasing (Identical VOUT Time)
Figure 9 shows two POLs with different slew rates in order to reach differing
final voltages at about the same time.
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Figure 10. Staggered or Sequential Phasing—Inclusive (Fixed Delays)
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Figure 11. Staggered or Sequential Phasing—Exclusive (Fixed Cascaded Delays)
Figures 10 and 11 show both delayed start up and delayed final voltages
for two converters. Figure 10 is called “Inclusive” because the later starting
POL finishes inside the earlier POL. The timing in Figure 10 is more easily built
using a combined digital sequence controller and the Sequence/Track pin.
Figure 11 is the same strategy as Figure 10 but with an “exclusive” timing
relationship staggered approximately the same at power-up and power-down.
Operation
To use the Sequence pin after power start-up stabilizes, apply a rising external
voltage to the Sequence input. As the voltage rises, the output voltage will
track the Sequence input (gain = 1). The output voltage will stop rising when
it reaches the normal set point for the converter. The Sequence input may op-
tionally continue to rise without any effect on the output. Keep the Sequence
input voltage below the converter’s input supply voltage.
Use a similar strategy on power down. The output voltage will stay constant
until the Sequence input falls below the set point.
Any strategy may be used to deliver the power up/down ramps. The circuits
below show simple RC networks but you may also use operational amplifiers,
D/A converters, etc.
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MDC_LSN2.B06 Page 11 of 15