D1U54 Datasheet, PDF (4/9 Pages) Murata Power Solutions Inc. – 54mm 1U Front End DC-DC Power Supply Converter

D1U54-D-650-12-HBxC Series
54mm 1U Front End DC-DC Power Supply Converter
STATUS AND CONTROL SIGNALS
Signal Name
I/O Description
Interface Details
INPUT_OK (DC Source) Output The signal output is driven high when the input source is available and within acceptable limits. Pulled up internally via 10K to 3.3Vdc.
The output is driven low to indicate loss of input power.
A logic high >2.0Vdc; A logic low <0.8Vdc
There is a minimum of 5ms pre-warning time before signal changes to a high impedance state or Driven low by internal CMOS buffer (open
is driven low to indicate loss of 12V. The power supply must ensure that this interface signal
drain output).
provides accurate status when DC power is lost.
PW_OK (Output OK)
Output The signal is asserted, driven high, by the power supply to indicate that all outputs are valid. If any Pulled up internally via 10K to 3.3Vdc.
of the outputs fail then this output will be hi-Z or driven low. The output is driven low to indicate A logic high >2.0Vdc; A logic low <0.8Vdc
that the Main output is outside of lower limit of regulation.
Driven low by internal CMOS buffer (open
drain output).
SMB_ALERT
Output The signal output is driven low to indicate that the power supply has detected a warning or fault Pulled up internally via 10K to 3.3Vdc.
(FAULT/WARNING)
and is intended to alert the system. This output must be driven high when the power is operating A logic high >2.0Vdc;A logic low <0.8Vdc
correctly (within specified limits).
Driven low by internal CMOS buffer (open
The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is
drain output).
removed.
PRESENT_L
Output The signal is used to detect the presence (installed) of a PSU by the host system. The signal is Passive connection to +VSB_Return.
(Power Supply Absent)
connected to PSU logic SGND within the power module.
A logic low <0.8Vdc
PS_ON
Input This signal is pulled up internally to the internal housekeeping supply (within the power supply). Pulled up internally via 10K to 3.3Vdc.
(Power Supply
The power supply main 12Vdc output will be enabled when this signal is pulled low to
A logic high >2.0Vdc
Enable/Disable
+VSB_Return.
A logic low <0.8Vdc
In the low state the signal input shall not source more than 1mA of current. The 12Vdc output will Input is via CMOS Schmitt trigger buffer.
be disabled when the input is driven higher than 2.4V, or open circuited. Cycling this signal shall
clear latched fault conditions.
PS_KILL
Input This signal is used during hot swap to disable the main output during hot swap extraction. The Pulled up internally via 10K to 3.3Vdc.
input is pulled up internally to the internal housekeeping supply (within the power supply).
A logic high >2.0Vdc; A logic low <0.8Vdc
The signal is provided on a short (lagging pin) and should be connected to +VSB_Return.
Input is via CMOS Schmitt trigger buffer.
ADDR (Address Select) Input An analogue input that is used to set the address of the internal slave devices (EEPROM and
DC voltage between the limits of 0 and
microprocessor) used for digital communications.
+3.3Vdc.
Connection of a suitable resistor to +VSB_Return, in conjunction with an internal resistor divider
chain, will configure the required address (see ADDR Address Selection table).
SCL (Serial Clock)
Both A serial clock line compatible with PMBus^TM Power Systems Management Protocol Part 1 – General VIL is 0.8V maximum
Requirements Rev 1.1.
VOL is 0.4V maximum when sinking 3mA
No additional internal capacitance is added that would affect the speed of the bus.
VIH is 2.1V minimum
The signal is provided with a series isolator device to disconnect the internal power supply bus in
the event that the power module is completely unpowered,
SDA (Serial Data)
Both A serial data line compatible with PMBus^TM Power Systems Management Protocol Part 1 – General VIL is 0.8V maximum
Requirements Rev 1.1.
VOL is 0.4V maximum when sinking 3mA
The signal is provided with a series isolator device to disconnect the internal power supply bus in VIH is 2.1V minimum
the event that the power module is completely unpowered,
V1_SENSE
Input Remote sense connections intended to be connected at and sense the voltage at the point of load. Compensation for up to 0.12Vdc total
V1SENSE_RTN
The voltage sense will interact with the internal module regulation loop to compensate for voltage connection drop (output and return
drops due to connection resistance between the output connector and the load.
connections).
If remote sense compensation is not required then the voltage shall be configured for local sense
by:
1. V1_SENSE directly connected to power blades 6 to 10 (inclusive)
2. V1_SENSE_RTN directly connected to power blades 1 to 5 (inclusive)
ISHARE
Bi- The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an Analogue voltage:
Directional input and/or an output (bi-directional analogue bus) as the voltage on the line controls the
+8V maximum; 10K to +12V_RTN
Analogue current share between sharing units. A power supply will respond to a change in this voltage
Bus but a power supply can also change the voltage depending on the load drawn from it. On a
single unit the voltage on the pin (and the common ISHARE bus would read 8VDC at 100% load
(module capability). For two identical units sharing the same 100% load this would read 4VDC
for perfect current sharing (i.e. 50% module load capability per unit).
www.murata-ps.com/support
D1U54-D-650-12-HBxC.A02 Page 4 of 9