D1U54-HD-1200-12-HA4C Datasheet, PDF (3/8 Pages) Murata Power Solutions Inc. – 54mm 1U Front End HVDC Power Supply Converter

D1U54-HD-1200-12-HA4C
54mm 1U Front End HVDC Power Supply Converter
STATUS AND CONTROL SIGNALS
Signal Name I/O
Description
HVDC_OK
(DC Source)
Output
The signal output is driven high when input source is available and within acceptable
limits. The output is driven low to indicate loss of input power.
There is a minimum of 1ms pre-warning time before the signal is driven low prior
to the PWR_OK signal going low. The power supply must ensure that this interface
signal provides accurate status when DC input power is lost.
PWOK (Output
OK)
SMB_ALERT
(FAULT/
WARNING)
PRESENT_L
(Power Supply
Absent)
Output
Output
Output
The signal is asserted, driven high, by the power supply to indicate that all outputs
are valid. If any of the outputs fail then this output will be hi-Z or driven low. The
output is driven low to indicate that the Main output is outside of lower limit of
regulation (11.4Vdc).
The signal output is driven low to indicate that the power supply has detected a
warning or fault and is intended to alert the system. This output must be driven high
when the power is operating correctly (within specified limits).
The signal will revert to a high level when the warning/fault stimulus (that caused
the alert) is removed.
The signal is used to detect the presence (installed) of a PSU by the host system. The
signal is connected to PSU logic SGND within the power module.
PS_ON
(Power Supply
Enable/Disable
PSKILL
This signal is pulled up internally to the internal housekeeping supply (within the
power supply). The power supply main 12Vdc output will be enabled when this signal
Input ^{is pulled low to +VSB_Return. In the low state the signal input shall not source more}
than 1mA of current. The 12Vdc output will be disabled when the input is driven
higher than 2.4V, or open circuited. Cycling this signal shall clear latched fault
conditions such as OVP.
This signal is used during hot swap to disable the main output during hot swap
extraction. The input is pulled up internally to the internal housekeeping supply
Input _{(within the power supply).}
The signal is provided on a short (lagging pin) and should be connected to +VSB_
Return.
ADDR (Address
Select)
SCL (Serial
Clock)
SDA (Serial
Data)
V1_SENSE
V1SENSE_RTN
An analog input that is used to set the address of the internal slave devices (EEPROM
Input ^{and microprocessor) used for digital communications.}
Connection of a suitable resistor to +VSB Return, in conjunction with an internal
resistor divider chain will configure the required address.
A serial clock line compatible with PMBusTM Power Systems Management Protocol
Part 1 – General Requirements Rev 1.1.
Both _{No additional internal capacitance is added that would affect the speed of the bus.}
The signal is provided with a series isolator device to disconnect the internal power
supply bus in the event that the power module is unpowered.
A serial data line compatible with PMBusTM Power Systems Management Protocol
Both ^{Part 1 – General Requirements Rev 1.1.}
The signal is provided with a series isolator device to disconnect the internal power
supply bus in the event that the power module is unpowered.
Remote sense connections intended to be connected at and sense the voltage at the
point of load.
The voltage sense will interact with the internal module regulation loop to
compensate for voltage drops due to connection resistance between the output
Input connector and the load.
If remote sense compensation is not required then the voltage can be configured for
local sense by:
V1_SENSE directly connected to power blades 6 to 10 (inclusive)
V1_SENSE_RTN directly connected to power blades 1 to 5
(inclusive)
Interface Details
Pulled up internally via 10K to VDD²
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer (open drain output).
Pulled up internally via 10K to VDD²
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer (open drain output).
Pulled up internally via 10K to VDD²
A logic high >2.0Vdc
A logic low <0.8Vdc
Driven low by internal CMOS buffer (open drain output).
Passive connection to +VSB_Return. A
logic low <0.8Vdc
Pulled up internally via 10K to VDD²
A logic high >2.0Vdc
DC voltage between the limits of 0 and VDD²
VIL is 0.8V maximum
VOL is 0.4V maximum when sinking 3mA VIH
is 2.1V minimum
VIL is 0.8V maximum
VOL is 0.4V maximum when sinking 3mA VIH
is 2.1V minimum
Compensation for up to 0.12Vdc total connection drop (output
and return connections).
The current sharing signal is connected between sharing units (forming an ISHARE
bus). It is an input and/or an output (bi-directional analog bus) as the voltage on the
ISHARE
Bi-Directional
Analogue
Bus
line controls the current share between sharing units. A power supply will respond to
a change in this voltage but a power supply can also change the voltage depending
on the load drawn from it. On a single unit the voltage on the pin (and the common
ISHARE bus would read 8VDC at 100% load (module capability). For two identical
Analogue voltage:
+8V maximum; 10K to +12V_RTN
units sharing the same 100% load this would read 4VDC for perfect current sharing
(i.e. 50% module load capability per unit).
2_{VDD is an internal voltage rail derived from VSB and an internal housekeeping rail (“diode ORed”) and is compatible with the voltage tolerances of VSB).}
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