MSK1911 Datasheet, PDF (4/6 Pages) M.S. Kennedy Corporation – HIGH PERFORMANCE, HIGH VOLTAGE VIDEO DISPLAY DRIVER

APPLICATION NOTES CON'T
VOFF CONTROL INPUT
The brightness (output offset) can be linearly adjusted by
applying a 0 to VREF DC voltage to the VOFF input pin. The
output quiescent voltage range is from approximately
(10mA)(200Ω) to (100mA)(200Ω) from +VHV. This control
voltage is normally generated by connecting the VOFF control
pin to a 5K potentiometer between VREF and ground. The VOFF
input pin should be bypassed with a 0.1µF capacitor to ground
placed as close as possible to the hybrid. This DC voltage can
be any stable system source.
Keep hybrid power dissipation in mind when adjusting the
output quiescent voltage. Practically all of the voltage is seen
across Rp. This power must be taken into account when high
Rp currents are used. If the quiescent level is set almost to
+VHV, the power dissipation will be minimal but the rise time
will suffer somewhat. If the quiescent level is set too far from
+VHV, the power dissipation will increase dramatically and the
output fall time will be limited. The output black level is obvi-
ously dependent on system requirements but a little experimen-
tation will strike the optimum balance between power dissipa-
tion and bandwidth. Total current through Rp should be limited
to less than 370mA when operating from power supplies greater
than 65V. The gain adjust alone can set the AC current to
250mA (ie: 250mApp=50Vpp/200Ω).
BLANK INPUT
The video input can be electrically disconnected from the
amplifier by applying a TTL high input to the blank pin. When
this occurs, the output will be set to approximately +VHV. The
VGAIN and VOFF control pins have little or no effect on the out-
put when it is in blank mode.
When the TTL compatible blank input is not used, the pin
must be connected to ground to enable the amplifier. The blank
input will float high when left unconnected which will disable
the video.
VREF OUTPUT
The MSK 1911 has an on board buffered DC zener reference
output. The VREF output is nominally 5.5V DC and has full
temperature test limits of 5.2V to 5.8V DC. This output is
provided for gain and offset adjustment and can source up to
4mA of current.
TRANSITION TIME MINIMIZATION
To achieve transition times of less than 3 nS with the MSK
1911, all stray and intrinsic capacitances must be compensated
for. Two external inductors can accomplish this task easily.
(Refer to the figure below). The 200Ω resistor (Rp) and the
capacitance of the output driver collector form a high frequency
pole which limits the rise and fall time. To compensate for this
effect, the series inductor (Lp) is placed in the circuit between
the internal Rp and +VHV. A good starting value for this induc-
tor is typically 100nH. Since all applications are slightly differ-
ent, it is likely that the designer will need to select this inductor
value to achieve the desired response. The second inductor
(L2) is only necessary when a series CRT isolation resistor (Rs)
is used. An inductor in the range of 30nH is placed in series
with the resistor to compensate for the pole formed by the
resistor and the CRT capacitance. The value of this inductor
may be varied as well for optimum response time.
THERMAL MANAGEMENT
The MSK 1911 package has mounting holes that allow the
user to connect the amplifier to a heat sink or chassis. Since
the package is electrically isolated from the internal circuitry,
mounting insulators are not required or desired for best thermal
performance.
The power dissipation of the amplifier depends mainly on
the load requirements, bandwidth, pixel size, black level and
the value of Rp. The following table illustrates an example:
Typical Power Consumption TC=25°C
Power Dissipation at +VHV=70V, RP=200Ω (Internal)
VO-VBLACK
Duty Cycle %
Total PD (Watts)
0
0
1.6
35
100
13.9
35
80
11.4
50
80
15.6
Display
Resolution
320 x 200
640 x 350
640 x 480
800 x 560
1024 x 900
1024 x 1024
1280 x 1024
1664 x 1200
2048 x 2048
4096 x 3300
RESOLUTION TABLE FOR TYPICAL CRT'S
Maximum
Pixel
Time
Minimum Pixel
Clock
Frequency
Required Rise Time
at CRT
Cathode
182nS
52nS
38nS
26nS
12.6nS
11nS
8.9nS
5.8nS
2.8nS
5MHz
19MHz
26MHz
38MHz
80MHz
90MHz
112MHz
170MHz
360MHz
60nS
17nS
12.5nS
8.6nS
4.2nS
3.7nS
2.9nS
1.9nS
1nS
860pS
1.2GHz
280pS
Required System
Bandwidth
(F-3dB)
6MHz
20MHz
28MHz
41MHz
84MHz
95MHz
120MHz
180MHz
380MHz
1.23GHz
All data assumes retrace time equal to 30% of frame time and a 60Hz refresh rate.
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Rev. D 8/00