MC68040RC25A Datasheet, PDF (88/442 Pages) Motorola, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
LOGICAL ADDRESS
31
S
PAGE FRAME
SUPERVISOR
BIT
LA31–LA12
12
0
PAGE OFFSET
PHYSICAL
SET SELECT
PA9–PA4
LINE 3
LINE 2
LINE 1
LINE 0
PA11–PA10
SET 0
SET 1
TAG STATUS D0 D1 D2 D3
ADDRESS
TRANSLATION
CACHE
PA31–PA12
SET 63
TAG STATUS D0 D1 D2 D3
TRANSLATED
PHYSICAL
ADDRESS
PA31–PA10
DATA OR
INSTRUCTION
MUX
COMPARATOR ⁰
3
2
1
HIT 3
HIT 2
HIT 1
HIT 0
LINE SELECT
HIT
LOGICAL OR
Figure 4-3. Caching Operation
Both caches contain circuitry to automatically determine which cache line in a set to use
for a new line. The cache controller locates the first invalid line and uses it; if no invalid
lines exist, then a pseudo-random replacement algorithm is used to select a valid line,
replacing it with the new line. Each cache contains a 2-bit counter, which is incremented
for each access to the cache. The instruction cache counter is incremented for each half-
line accessed in the instruction cache. The data cache counter is incremented for each
half-line accessed during reads, for each full line accessed during writes in copyback
mode, and for each bus transfer resulting from a write in write-through mode. When a
miss occurs and all four lines in the set are valid, the line pointed to by the current counter
value is replaced, after which the counter is incremented.
4-4
M68040 USER'S MANUAL
MOTOROLA
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