MC68040RC25A Datasheet, PDF (131/442 Pages) Motorola, Inc – Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.
Table 6-2. Boundary Scan Bit Definitions (Concluded)
Pin/Cell
Bit Cell Type Name
148
I.Pin
SIZ1
149 O.Latch LOCK
Output
Pin Type Ctrl Cell
I/O
io.0
TS-Output ² io.1
Pin/Cell
Bit Cell Type Name
166 O.Latch
TA
167
I.Pin
TA
Pin Type
I/O2
I/O
Output
Ctrl Cell
io.2
io.2
150 IO.Ctl
io.ab
—
(Note 4)
168
I.Pin
TEA
Input
—
151 IO.Ctl
io.db
—
(Note 4)
169
I.Pin
BG
152 O.Latch
MI
Output2 (Note 3)
170
I.Pin
SC1
153 O.Latch
BR
Output2 (Note 3)
171
I.Pin
SC0
Input
—
Input
—
Input
—
154 IO.Ctl
io.2
—
(Note 4)
172
I.Pin
TBI
Input
—
155 IO.Ctl
io.1
—
(Note 4)
173
I.Pin
AVEC
Input
—
156 IO.Ctl
io.0
157 O.Latch
TS
—
(Note 4)
I/O2
io.0
174
I.Pin
175
I.Pin
TCI
DLE ⁵
Input
—
Input
—
158
I.Pin
TS
159 O.Latch
BB
I/O
io.0
I/O2
io.1
176
I.Pin
177
I.Pin
PCLK
BCLK
Input
—
Input
—
160
I.Pin
161 O.Latch
162 O.Latch
163 O.Latch
164 O.Latch
165 O.Latch
BB
TIP
PST3
PST2
PST1
PST0
I/O
io.1
TS-Output ² io.1
Output2 (Note 3)
Output2 (Note 3)
Output2 (Note 3)
Output2 (Note 3)
178
I.Pin
179
I.Pin
180
I.Pin
181
I.Pin
182
I.Pin
183
I.Pin
IPL0
IPL1
IPL2
RSTI
CDIS
MDIS ⁶
Input
—
Input
—
Input
—
Input
—
Input
—
Input
—
NOTES:
1. I.Pin, IO.Ctl, and O.Latch are equivalent to the BSDL descriptions: BC_4, BC_2, and BC_2, respectively.
2. Boundary scan register bit positions that are used during the drive control (DRVCTL.X) instructions.
3. These output-only cells can be turned off (high impedance) by using the HIGHZ instruction.
4. All of the control signals (IO.Ctl) are cleared in the test-logic-reset state.
5. Renamed JS0 on the MC68LC040 and MC68EC040.
6. Renamed JS1 on the MC68EC040.
6.4 RESTRICTIONS
The test logic is implemented using static logic design, and TCK can be stopped in either
a high or low state without loss of data. The system logic, however, includes considerable
dynamic logic. For this reason, the system clocks (PCLK and BCLK) cannot be stopped or
allowed to run slower than the specified frequency except when the EXTEST, HIGHZ,
DRVCTL.T, or SHUTDOWN instructions have been properly invoked.
PCLK and BCLK must be kept running for two additional BCLK periods upon initial entry
into any of the four instructions, EXTEST, HIGHZ, DRVCTL.T, or SHUTDOWN. This
restriction is necessary to allow time for an internal reset to propagate through an internal
synchronizer. After this period, the user has complete time-domain freedom with the two
system clock pins. After any of the four instructions has been properly entered, these
instructions can be executed in any order without a time-domain clocking restriction.
Entering any instruction other than one of these four requires that the system clocks be
6-12
M68040 USER’S MANUAL
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