56F8322 Datasheet, PDF (88/128 Pages) Motorola, Inc – 56F8322 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
DQ
D-FLOP
C
56800E
Reprogrammable
Disable
DQ
D-FLOP
STOP_DIS
Clock
Select
RESET
CR
Note: Wait disable
circuit is similar
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For
lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly
before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut
down, the 56800E system clock must be set equal to the prescaler output.
Some applications require the 56800E STOP and WAIT instructions be disabled. To disable those
instructions, write to the SIM control register (SIM_CONTROL) described in Section 6.5.1 . This
procedure can be on either a permanent or temporary basis. Permanently assigned applications last
only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin
and the Power-On Reset (POR). The two synchronous sources are the software reset, which is
generated within the SIM itself, by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is
sequenced to permit proper operation of the device. A POR reset is declared when RESET is
removed and any of the three voltage detectors (1.8V POR, 2.2V core voltage, or 2.7V I/O voltage)
indicate a low supply voltage condition. POR will continue to be asserted until all voltage detectors
indicate a stable supply is available (note that as power is removed POR is not declared until the
1.8V core voltage threshold is reached.) A POR reset is then extended for 64 clock cycles to permit
stabilization of the clock source, followed by a 32 clock window in which SIM clocking is initiated.
It is then followed by a 32 clock window in which peripherals are released to implement Flash
security, and, finally, followed by a 32 clock window in which the core is initialized. After
completion of the described reset sequence, application code will begin execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the
system clock.
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