56F8322 Datasheet, PDF (1/128 Pages) Motorola, Inc – 56F8322 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
MC56F8322/D
Rev. 9.0, 06/2004
56F8322
Preliminary Technical Data
56F8322 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• One Quadrature Decoder
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Two 3-channel 12-bit ADCs
• Up to 21 GPIO lines
• Temperature Sensor
• 48-pin LQFP Package
RESET
4
V_CAP V_DD
2
4
V_SS
4
V_DDA V_SSA
6 _{PWM Outputs}
Fault Inputs
PWMA
or SPI1 or
GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
3
AD0
PAB
PDB
CDBR
CDBW
3
AD1
3
VREF
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
XDB2
XAB1
XAB2
TEMP_SENSE 4K x 16 Boot
PAB
Flash
PDB
4
Quadrature
Decoder 0 or
Quad
Data Memory
4K x 16 Flash
4K x 16 RAM
CDBR
CDBW
Timer A
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Quad Timer C
2
or SCI0
or GPIOC _Decoding
Peripheral
Device Selects
RW
Control
IPWDB IPRDB
2
FlexCAN Peripherals
or GPIOC
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Interrupt
Watchdog Controller
IRQA
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
*Includes On-Chip
Relaxation Oscillator
56F8322 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
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