56F8322 Datasheet, PDF (74/128 Pages) Motorola, Inc – 56F8322 16-bit Hybrid Controller

Freescale Semiconductor, Inc.
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand
the various chip operating modes and take appropriate action. These are:
• Reset Mode, which has two submodes:
— Total Reset Mode
– 56800E Core and all peripherals are reset
— Core-Only Reset Mode
– 56800E Core in reset, peripherals are active
– This mode is required to provide the on-chip Flash interface module time to load data from
Flash into FM registers
• Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip
operation.
• Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP
and PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to
disable any motor from being driven; see the PWM chapter in the 56F8300 Peripheral User
Manual for details.
• Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All
other peripherals continue to run.
• Stop Mode
56800E, memory and most peripheral clocks are shut down. Optionally, the COP and CAN can be
stopped. For lowest power consumption in Stop mode, the PLL can be shut down. This must be
done explicitly before entering Stop mode, since there is no automatic mechanism for this. The
CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is
not fully functional in Stop mode.
6.4 Operating Mode Register
Bit
15 14 13 12 11 10 9
8
76
5
4
3
2
1
0
NL
CM XP SD
R
SA EX
0
MB MA
Type
R/W
R/W R/W R/W R/W R/W R/W
R/W R/W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-1 OMR
See Section 4.2 for detailed information on how the Operating Mode Register (OMR) MA and
MB bits operate in this device. The EX bit is not functional in this device since there is no external
memory interface. For all other bits, see the 56F8300 Peripheral User Manual.
Note:
The OMR is not a Memory Map register; it is directly accessible in code through the acronym
OMR.
74
56F8322 Technical Data
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