DSP56L307 Datasheet, PDF (60/108 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor, Inc.
AC Electrical Characteristics
2.5.7 SCI Timing
Table 2-18. SCI Timings
100 MHz 160 MHz
No.
Characteristics¹
Symbol
Expression
Unit
Min Max Min Max
400 Synchronous clock cycle
401 Clock low period
402 Clock high period
403 Output data setup to clock falling edge
(internal clock)
t_SCC2
8 × T_C
80 — 50 — ns
t_SCC/2 − 10.0
30.0 — 15.0 — ns
t_SCC/2 − 10.0
30.0 — 15.0 — ns
t_SCC/4 + 0.5 × T_C −10.0 8.0 — 0.0 — ns
404 Output data hold after clock rising edge
(internal clock)
t_SCC/4 − 0.5 × T_C
15.0 — 9.4 — ns
405 Input data setup time before clock rising
edge (internal clock)
t_SCC/4 + 0.5 × T_C + 25.0 50.0 — 40.6 — ns
406 Input data not valid before clock rising
edge (internal clock)
t_SCC/4 + 0.5 × T_C − 5.5
— 19.5 — 10.1 ns
407 Clock falling edge to output data valid
(external clock)
— 32.0 — 32.0 ns
408 Output data hold after clock rising edge
(external clock)
T_C + 8.0
18.0 — 14.3 — ns
409 Input data setup time before clock rising
edge (external clock)
0.0 — 0.0 — ns
410 Input data hold time after clock rising edge
(external clock)
411 Asynchronous clock cycle
412 Clock low period
413 Clock high period
414 Output data setup to clock rising edge
(internal clock)
t_ACC3
64 × T_C
t_ACC/2 − 10.0
t_ACC/2 − 10.0
t_ACC/2 − 30.0
9.0 — 9.0 — ns
640.0 — 400.0 — ns
310.0 — 190.0 — ns
310.0 — 190.0 — ns
290.0 — 170.0 — ns
415 Output data hold after clock rising edge
(internal clock)
t_ACC/2 − 30.0
290.0 — 170.0 — ns
Notes: 1. V_CCQH = 3.3 V ± 0.3 V, V_CC = 1.8 V ± 0.1 V; T_J = –40°C to +100 °C, C_L = 50 pF.
2. t_SCC = synchronous clock cycle time (for internal clock, t_SCC is determined by the SCI clock control register and
T_C).
3. t_ACC = asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t_ACC is determined by
the SCI clock control register and T_C).
2-36
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