DSP56L307 Datasheet, PDF (11/108 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

Freescale Semiconductor, Inc.
External Memory Expansion Port (Port A)
1.6 External Memory Expansion Port (Port A)
Note: When the DSP56L307 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A[0–17], D[0–23], AA0/RAS0–AA3/RAS3,
RD, WR, BB, CAS.
1.6.1 External Address Bus
Signal
Name
A[0–17]
Table 1-6. External Address Bus Signals
Type
Output
State During
Reset, Stop, or
Wait
Tri-stated
Signal Description
Address Bus—When the DSP is the bus master, A[0–17] are
active-high outputs that specify the address for external
program and data memory accesses. Otherwise, the signals
are tri-stated. To minimize power dissipation, A[0–17] do not
change state when external memory spaces are not being
accessed.
1.6.2 External Data Bus
Table 1-7. External Data Bus Signals
Signal
Name
Type
D[0–23] Input/ Output
State
During
Reset
Ignored
Input
State
During
Stop or
Wait
Signal Description
Last state:
Input:
Ignored
Output:
Last value
Data Bus—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] drivers are tri-stated. If the last
state is output, these lines have weak keepers that maintain
the last output state even when all drivers are tri-stated.
1-5
For More Information On This Product,
Go to: www.freescale.com