DSP56L307 Datasheet, PDF (1/108 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

Technical Data
Advance Information
DSP56L307/D
Rev. 5, 6/2004
24-Bit Digital Signal
Processor
Freescale Semiconductor, Inc.
The DSP56L307 is
intended for
applications requiring
a large amount of
internal memory, such
as networking and
wireless infrastructure
applications. The
EFCOP can accelerate
general filtering
applications, such as
echo-cancellation
applications,
correlation, and
general-purpose
convolution-based
algorithms.
3
16
66
Memory Expansion Area
SCI
Triple
Timer
HI08
ESSI
EFCOP
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Peripheral
Expansion Area
Internal
Data
Bus
Switch
Clock
Generator
PLL
Program
Interrupt
Controller
EXTAL
XTAL
RESET
PINIT/NMI
PCAP
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
RAM
16 K × 24 bits
or
15 K × 24 bits
and
Instruction
Cache
1024 × 24 bits
X Data
RAM
24 K × 24 bits
Y Data
RAM
24 K × 24 bits
YAB
XAB
PAB
DAB
External
Address
Bus
Switch
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
External
Bus
Interface
and
I - Cache
Control
13
Control
External
Data
Bus
Switch
24
Data
Power
Management
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
JTAG
OnCE™
5
DE
Figure 1. DSP56L307 Block Diagram
What’s New?
Rev. 5 updates the
example clock input
circuits in Figure 2-1.
The Motorola DSP56L307, a member of the
DSP56300 Digital Signal Processor (DSP) family,
supports network applications with general
filtering operations. The Enhanced Filter
Coprocessor (EFCOP) executes filter algorithms in
parallel with core operations, enhancing signal
quality with no impact on channel throughput or
total channels supported. The result is increased
overall performance. Like the other DSP56300
family members, the DSP56L307 uses a
high-performance, single-clock-cycle-per-
instruction engine (DSP56000 code-compatible), a
barrel shifter, 24-bit addressing, an instruction
cache, and a direct memory access (DMA)
controller (see Figure 1). The DSP56L307
performs at 160 million instructions per second
(MIPS), attaining 290 MIPS when the EFCOP is in
use. It operates with an internal 160 MHz clock
with a 1.8 volt core and independent 3.3 volt
input/output (I/O) power.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
For More Information On This Product,
Go to: www.freescale.com