MC88PL117 Datasheet, PDF (6/11 Pages) Motorola, Inc – CMOS PLL CLOCK DRIVER

MC88PL117
PRELIMINARY AC ELECTRICAL CHARACTERISTICS (TA = 0 to 70°C, VCC = 5.0V ±5%)
Target Specifications
Symbol
Parameter
Min
Max
Unit
Condition
tskewr
Output–to–Output Skew (Same Frequency,
Coincident Rising Edges)
500
ps 50Ω Load²
tskewrall
Output–to–Output Skew (Any Frequency,
Coincident Rising Edges, Q0–Q13, QFEED)
500
ps 50Ω Load²
tskewp
tr/tf
tPULSE
Part–to–Part Skew¹
1.0
ns 50Ω Load²
Output Rise/Fall Time (0.8 to 2.0V)
0.15
1.0
ns 50Ω Load²
Output Pulse Width, All Outputs² (Measured at 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5
ns
50Ω Load²
VCC/2)
tpd
SYNC Input to
fSYNC=15MHz
–200
FEEDBACK Delay
fSYNC=20MHz
–200
fSYNC=25MHz
–100
fSYNC=30MHz
0
400
ps Feedback=Q,Q/2
400
500
600
fSYNC=15MHz
–50
550
Feedback=Q/4
JitterCC
Cycle–to–Cycle Jitter (Clock Period Stability)
fMAX
Maximum Output Frequency for 2X_Q Outputs
8
fMAX
Maximum Output Frequency for Q Outputs
4
fMAX
Maximum Output Frequency for Q/2 Outputs
2
±250
120
60
30
ps
MHz
MHz
MHz
50Ω Load²
50Ω Load²
50Ω Load²
tskew_âˆ
Phase Accuracy of Q∅ versus Q or Q/2
Phase Offset – 750 Phase Offset + 250 ps
1. This assumes that each device is running off of the same clock source with zero skew between clock source signals. A small amount of negative
offset may be present between SYNC and FEEDBACK (tPD Spec).
2. 50Ω load terminated to VCC/2.
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6