MC88PL117 Datasheet, PDF (3/11 Pages) Motorola, Inc – CMOS PLL CLOCK DRIVER

SYNC0
0
SYNC1
1
REF_SEL
FEEDBACK
PLL_EN
LOCK INDICATOR
CIRCUITRY
EXTERNAL
FILTER PIN
LOCK
PFD
CH
PUMP
VCO
Disable
01
OPT2
OPT1
OPT0
OUTPUT
FREQUENCY
AND PHASE
CONTROL
LOGIC
MC88PL117
DQ
Q0
R
POWER–ON
RESET
MULT1
MULT0
∅2
∅1
∅0
OE/MR
FEEDBACK
LOGIC
PHASE DELAY
LOGIC
DQ
R
DQ
R
DQ
R
MC88PL117 Block Diagram (Logical Representation)
Q13
QFEED
Q∅
TIMING SOLUTIONS
3
BR1333 — Rev 6
MOTOROLA