EB212 Datasheet, PDF (6/8 Pages) Motorola, Inc – Using Data Sheet Impedances for RF LDMOS Devices

EB212
Freescale Semiconductor, Inc.
Figure 12. Optimization Layout for Input Matching Network of the MRF21180
Figure 12 shows the following major blocks of interest:
• General Matching Network
• DC Feed blocks 1 and 2
• MSTEP blocks
• Three - port user defined sub - circuit (balun)
• Two - port *.s1p
The General Matching Network shown in Figure 12
represents the typical and realizable circuit elements used in
designing a good first - pass design. The network topology
shown is not constrained to the one in Figure 12. However, this
topology is a typical design.
The two DC Feed blocks and MSTEP blocks shown are
similar to those shown in Figure 7 for single - ended devices
and are identical in function.
The three - port sub - circuit in Figure 12 can be an
ADS - designed balun (the user can design) or represented as
an *.s3p file generated using Sonnet or a similar
electro - magnetic simulation software.
The two- port S1P data block file represents the conjugate
of the measured impedance data for the MRF21180. The
block has two ports that present the conjugated impedance
and a third port for reference to ground.
CONCLUSION
This engineering bulletin gives a brief explanation of how to
implement a matching structure based on measured
impedance data. Although there are other solutions, using this
methodology will provide a designer with a good
approximation of a final design.
REFERENCE
J. J. Bouny, “Impedance Measurements for High Power RF
Transistors Using the TRL Method,” Microwave Journal,
October 1999.
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