EB212 Datasheet, PDF (3/8 Pages) Motorola, Inc – Using Data Sheet Impedances for RF LDMOS Devices

Freescale Semiconductor, Inc.
EB212
S₁₁ < −30 dB
50 Ω
Matching
Network
MSTEP
b
a
Z (Device)
Z*_{Data Sheet}
Figure 6. Generalized Schematic Used to Optimize Matching Network
Note: When using the impedances presented in this
engineering bulletin, the designer should assume that the
impedances are based on a 50 Ω system, even though some
Smith charts may use normalized impedances of different
values for display purposes only.
The block diagram in Figure 6 has a generic matching circuit
that will be used for an optimization of the first- pass matching
network.
The MRF19125 impedance data from Figure 5 is used to
illustrate this as a practical example for developing a
first - pass matching network as shown in Figure 8. A few key
details are as follows:
• The S1P file was used as a two - port (reference is the
grounded port) device and its file name formatting.
• The DC_Block and BYPASS capacitors are shown with
generic values.
• The MLIN, ideally, should have an electrical length of λ / 4
from the DC feed - DUT junction.
• The simplified C_BYPASS capacitor elements placement
should be as close as possible to the length of the MLIN.
Note: A sample matching network is shown, but this may be
changed to a topology of any configuration.
The MSTEP block, discussed earlier, must be placed
between the device and the first matching element MLIN (see
Figures 6, 8, 10 and 11 for details on placement). This block
is important because it is used to determine the difference
between the reference plane width and the copper lead pad
width. If these values are not the same, there will be an
impedance discontinuity. The MSTEP is specified by its width
values (“a” and “b”). The value for Dimension “a” is found in the
package dimension section of the data sheet. Dimension “b”
is the width of the copper pad on the PCB that the lead is to
be seated on.
The MTEE, another ADS block, is used to connect the bias
feed (see Figure 7). The MTEE has design rules that are
violated in typically optimized fixture layouts. A simple nodal
connection has been found to be sufficient to simulate this
accurately. However, it is recommended to use the MTEE
within its usage constraints if at all possible.
So far the impedance data has been acquired, conjugated
and reinserted into an *.s1p file. The next step is to run an
S - parameter optimization simulation using the SP1 block, as
illustrated in Figure 8. Then the matching network should be
tuned to an S_1,1 of at least - 30 dB (or as low as possible),
resulting in a first - pass input match circuit. This process
should be repeated using the output impedances to generate
the output match. Finally, the matching networks are ready for
realization on a printed circuit board.
MTEE Design Rules
Symbol
Illustration
1
2
2
W1 1
3
W2
3
W1 = conductor width at pin 1, in specified units
W2 = conductor width at pin 2, in specified units
W3 = conductor width at pin 3, in specified units
W3
W (largest) / W (smallest) ≤ 5
W (largest) and W (smallest) are the largest and smallest
widths among W1, W2 and W3
0.05 x H ≤ W1 ≤ 20 x H
0.05 x H ≤ W2 ≤ 20 x H
0.05 x H ≤ W3 ≤ 20 x H
ε_r ≤ 20
f (GHz) x H (mm) ≤ 0.4 x Z_o
Z_o is the characteristic impedance
Figure 7. Design Constraints for the MTEE Block
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3
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