MC88LV926 Datasheet, PDF (5/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL 68060 CLOCK DRIVER

MC88LV926
AC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%)
Symbol
tRISE/FALL¹
All Outputs
tRISE/FALL¹
2X_Q Output
tpulse _width(a)¹
(Q0, Q1, Q2, Q3)
Parameter
Rise/Fall Time, into 50Ω Load
Rise/Fall Time into a 50Ω Load
Output Pulse Width
Q0, Q1, Q2, Q3 at 1.65V
tpulse _width(b)¹
(2X_Q Output)
Output Pulse Width
2X_Q at 1.65V
tSKEWr^1,2
(Rising)
Output–to–Output Skew
Between Outputs Q0–Q2
(Rising Edge Only)
tSKEWf^1,2
(Falling)
Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)
tSKEWall^1,2
Output–to–Output Skew
2X_Q, Q0–Q2, Q3
Mimimum
0.3
0.5
0.5tcycle – 0.5
0.5tcycle – 0.5
—
—
—
Maximum
1.6
1.6
0.5tcycle + 0.5
0.5tcycle + 0.5
500
1.0
750
Unit
Condition
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
ns tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
ns 50Ω Load Terminated to
VCC/2 (See Application
Note 3)
ns 50Ω Load Terminated to
VCC/2 (See Application
Note 3)
ps Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 5.)
ns Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 5.)
ps Into a 50Ω Load
Terminated to VCC/2
(See Timing Diagram in
Figure 5.)
tSKEW QCLKEN Output–to–Output Skew
QCLKEN to 2X_Q
2X_Q = 50MHz
9.7⁶
2X_Q = 66MHz
7.0⁶
tLOCK³
Phase–Lock Acquisition Time,
1
All Outputs to SYNC Input
ns Into a 50Ω Load
—
Terminated to VCC/2
(See Timing Diagram in
Figure 5.)
10
ms
tPHL MR – Q
Propagation Delay,
1.5
MR to Any Output (High–Low)
tREC, MR to
Reset Recovery Time rising MR edge
9
SYNC⁵
to falling SYNC edge
tW, MR LOW⁵
Minimum Pulse Width, MR input Low
5
tW, RST_IN LOW Minimum Pulse Width, RST_IN Low
10
tPZL
Output Enable Time
1.5
RST_IN Low to RST_OUT Low
13.5
ns Into a 50Ω Load
Terminated to VCC/2
—
ns
—
ns
—
ns When in Phase–Lock
16.5
ns See Application
Note 5
tPLZ
Output Enable Time
RST_IN High to RST_OUT High Z
1016 ‘Q’ Cycles 1024 ‘Q’ Cycles ns
(508 Q/2 Cycles) (512 Q/2 Cycles)
See Application
Note 5
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF.
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Specification is valid only when the PLL_EN pin is low.
6. Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.
TIMING SOLUTIONS
5
BR1333 — REV 5
MOTOROLA