MC88LV926 Datasheet, PDF (4/10 Pages) Motorola, Inc – LOW SKEW CMOS PLL 68060 CLOCK DRIVER

MC88LV926
RST_OUT
RST_IN
SYNC1
PLL_EN
MR
LOCK INDICATOR
RESET_OUT
PFD
CH
PUMP
VCO
01
÷8
POWER–ON
RESET
DELAY
Q
÷2
R
Q
÷4
R
Q
÷4
R
Q
÷4
R
Q
÷4
R
÷4
R
Figure 1. MC88LV926 Logic Block Diagram
2X_Q
Q0
Q1
Q2
Q3
CLKEN
SYNC INPUT TIMING REQUIREMENTS
Symbol
tRISE/FALL
SYNC Input
tCYCLE,
SYNC Input
Duty Cycle
Parameter
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
Input Clock Period
SYNC Input
Duty Cycle, SYNC Input
Minimum
Maximum
Unit
—
5.0
ns
1
200
ns
f2X_Qń4
50% ± 25%
FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V or 5.0V ±5%)
Symbol
Fmax (2X_Q)
Fmax (‘Q’)
Parameter
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q3 Outputs
Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition.
Guaranteed Minimum
66
33
Unit
MHz
MHz
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — REV 5