MCM63F837 Datasheet, PDF (20/28 Pages) Motorola, Inc – 256K x 36 and 512K x 18 Bit Flow–Through BurstRAM Synchronous Fast Static RAM

Freescale Semiconductor, Inc.
TAP CONTROLLER TIMING
Parameter
Symbol
Min
Max
TCK Cycle Time
tTHTH
60
—
TCK Clock High Time
tTH
25
—
TCK Clock Low Time
tTL
25
—
TDO Access Time
tTLQV
1
10
TRST Pulse Width
tTSRT
40
—
Setup Times
Capture
tCS
5
—
TDI
tDVTH
5
TMS
tMVTH
5
Hold Times
Capture
tCH
13
—
TDI
tTHDX
14
TMS
tTHMX
14
NOTE:
1. tCS and tCH define the minimum pauses in RAM I/O transitions to assure accurate pad data capture.
Unit Notes
ns
ns
ns
ns
ns
ns
1
ns
1
TEST CLOCK
(TCK)
tTHTL
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
TEST DATA OUT
(TDO)
TAP CONTROLLER TIMING DIAGRAM
tTHTH
tTLTH
tMVTH
tDVTH
tTHMX
tTHDX
tTLQV
MCM63F837•MCM63F919
20
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MOTOROLA FAST SRAM