MC68341UMAD Datasheet, PDF (18/21 Pages) Motorola, Inc – Integrated Processor Users Manual

edges of the clock signals - the PLL phase locks the falling edge of CLKOUT to the falling edge on EXTCLK.
70. Data Setup Time for 3.3V
On page 12-9, electrical specification #27 (Data Setup to CLKOUT Low) for 3.3V product only has been
changed from 5ns to 8ns.
71. UWE and LWE Signals
In Figure 12-3 on page 12-12, UWE and LWE will assert for the write buys cycle with the same timing as DS.
In the fast termination write cycle in Figure 12-5 on page 12-14, UWE and LWE (not shown) remain negated
like DS.
72. Serial Module Specs
Note 1 on page 12-25 should reference synchronous operation, not asynchronous.
73. Ordering Information
Replace the the ordering information table in Section 11 with the following ordering information.
Supply
Voltage
Package Type
5.0 V
5.0 V
3.3 V
Plastic Quad Flat Pack
FT Suffix
Plastic Quad Flat Pack
FT Suffix
Plastic Quad Flat Pack
FT Suffix
Frequency
(MHz)
0 – 25
0 – 16.78
0 – 16.78
Temperature
0°C to +70°C
-40° to 85°C
0°C to +70°C
-40° to 85°C
0°C to +70°C
Order Number
XC68341FT25
XC68341CFT25
XC68341FT16
XC68341CFT16
XC68341FT16V
74. Upper and Lower Data Strobes
In paragraph 3.2.8 page 3-6, change (D15–D0) to (D15–D8) and (D8–D0) to (D7–D0).
75. Figure 3-2
Change Note 1 to reference MC68341 instead of MC68340.
76. Figure 4-8
The Periodic Interrupt Control Register (PICR) and Periodic Interrupt Timing Register (PITR) should be 1 word
instead of 2 bytes. Disregard the Scale Select Register.
77. Page 4-24
Refer to 4-17 for more information on the AVEC-Automatic Vector Responsibility.
78. Page 4-48
The lake at the start of the code should be INIT341 instead of INIT340.
MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
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