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MC68341UMAD Datasheet, PDF (14/21 Pages) Motorola, Inc – Integrated Processor Users Manual | |||
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51. Single Address Enable
6-33 SE-Single Address Enable: The note âused for intermodule DMAâ should be for the SE=1 case. The
68341 does not support intermodule single address transfers, so the SE bit should always be programmed to
â0â.
52. Code Examples - Immediate Addressing Mode
On pages 6-40 through 6-44 make the following change as shown for each occurrence of SARADD, DARADD,
and NUMBYTE (change to immediate addressing mode for source operand):
MOVE.L SARADD,DMASAR1(A0) should be MOVE.L #SARADD,DMASAR1(A0).
MOVE.L DARADD,DMADAR1(A0) should be MOVE.L #DARADD,DMADAR1(A0).
MOVE.L NUMBYTE,DMABTC1(A0) should be MOVE.L #NUMBYTE,DMABTC1(A0).
53. Serial Oscillator Problems with DMA activity
Add to the Crystal Input or External Clock (X1) section on page 7-5: A high DREQ1 request rate (greater than
1MHz) with excessive undershoot on DREQ1 can result in internal signal coupling to the serial module oscil-
lator X1 pin, damping out oscillation. Avoid routing DREQ1 near the serial oscillator external components, and
use termination techniques such as series termination of the DREQ1 driver (start with 33â¦) to limit edge rate
of the signal and accompanying undershoot.
54. Additional Note on RTSx operation details
Add to the RTSA and RTSB descriptions on page 7-6: The RTSx outputs are active low signals - they drive a
logic â0â when set, and a logic â1â when cleared.
RTSx can be set (output logic level 0) by any of the following:
⢠Writing a â1â to the corresponding bit in the OPSET register $71E
⢠Issuing an âAssert RTSâ command using command register CR
⢠If RxRTS=1, set by receiver FIFO transition from FULL to not-FULL
RTSx can be cleared (output logic level 1) by any of the following:
⢠Hardware reset of the serial module
⢠Writing a â1â to the corresponding bit in the OPRESET register $71F
⢠Issuing a âNegate RTSâ command using command register CR
⢠If RxRTS=1, cleared by receiver FIFO transition from not-FULL to FULL
⢠If TxRTS=1, cleared by completion of last character, including transmission of stop bits
55. Serial Frequency Restriction
On page 7-8, place the following notes at the end of Section 7.3.1 Baud Rate Generator:
The current implementation of the serial module restricts the minimum CLKOUT frequency at which the baud
rate generators can be used to approximately 8.3MHz. Operation below this frequency results in a synchro-
nized internal clock which is at a lower frequency than the X1 input, which then results in incorrect baud rates.
One method to extend the minimum CLKOUT frequency is to reduce the X1 frequency by powers of 2 as
shown in the table below. The corresponding baud rates selected by the clock select register programming are
MOTOROLA
MC68341 USERâS MANUAL ADDENDUM
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