MTD20P03HDL Datasheet, PDF (1/12 Pages) Motorola, Inc – TMOS POWER FET LOGIC LEVEL 19 AMPERES 30 VOLTS RDS(on) = 0.099 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD20P03HDL/D
™ Designer's Data Sheet
HDTMOS E-FET.™
High Density Power FET
DPAK for Surface Mount
P–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
™
D
S
MTD20P03HDL
Motorola Preferred Device
TMOS POWER FET
LOGIC LEVEL
19 AMPERES
30 VOLTS
RDS(on) = 0.099 OHM
CASE 369A–13, Style 2
DPAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
30
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
30
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
±15
Vdc
VGSM
± 20
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
19
Adc
ID
12
IDM
57
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
PD
75
Watts
0.6
W/°C
1.75
Operating and Storage Temperature Range
TJ, Tstg – 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 19 Apk, L = 1.1 mH, RG = 25 Ω)
EAS
200
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R_θJC
R_θJA
R_θJA
1.67
°C/W
100
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
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