MTD20N06V Datasheet, PDF (1/10 Pages) Motorola, Inc – TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.080 OHM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MTD20N06V/D
™ Designer's Data Sheet
TMOS V™
Power Field Effect Transistor
DPAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
G
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors
MTD20N06V
TMOS POWER FET
20 AMPERES
60 VOLTS
RDS(on) = 0.080 OHM
TM
D
S
CASE 369A–13, Style 2
DPAK Surface Mount
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 MΩ)
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)
VDSS
60
Vdc
VDGR
60
Vdc
VGS
± 20
Vdc
VGSM
± 25
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
20
Adc
ID
13
IDM
70
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C(1)
PD
60
Watts
0.4
W/°C
2.1
Watts
Operating and Storage Temperature Range
TJ, Tstg – 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
200
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient(1)
R_θJC
2.5
°C/W
R_θJA
100
R_θJA
71.4
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
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