MC54-74HC595A Datasheet, PDF (1/10 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs
High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
SERIAL
DATA
INPUT
A ¹⁴
LOGIC DIAGRAM
SHIFT
REGISTER
LATCH
SHIFT 11
CLOCK
RESET ¹⁰
LATCH 12
CLOCK
OUTPUT 13
ENABLE
VCC = PIN 16
GND = PIN 8
15 _QA
1 _QB
2 _QC
3 _QD
4 _QE
5 _QF
6 _QG
7 _QH
PARALLEL
DATA
OUTPUTS
9 _SQH
SERIAL
DATA
OUTPUT
MC54/74HC595A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
QB 1
QC 2
QD 3
QE 4
QF 5
QG 6
QH 7
GND 8
16 VCC
15 QA
14 A
13 OUTPUT ENABLE
12 LATCH CLOCK
11 SHIFT CLOCK
10 RESET
9 SQH
3/97
© Motorola, Inc. 1997
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