74HC541A Datasheet, PDF (1/6 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC54/74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal non–inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock drivers, and
other bus–oriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed active–low output enables.
The HC541A is similar in function to the HC540A, which has inverting
outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
MC54/74HC541A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
Data
Inputs
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
LOGIC DIAGRAM
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
Non–Inverting
Outputs
13
Y6
FUNCTION TABLE
Inputs
OE1 OE2 A
Output Y
L
L
L
L
L
L
H
H
HXX
Z
XHX
Z
Z = High Impedance
X = Don’t Care
8
A7
12
Y7
9
A8
11
Y8
Output
Enables
OE1 ¹
OE2
19
PIN 20 = VCC
PIN 10 = GND
Pinout: 20–Lead Packages (Top View)
VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11
10/95
© Motorola, Inc. 1995
1 2 3 4 5 6 7 8 9 10
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
3–1
REV 1