PS22A74 Datasheet, PDF (8/11 Pages) Mitsubishi Electric Semiconductor – Dual-In-Line Package Intelligent Power Module

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PS22A74
TRANSFER MOLDING TYPE
INSULATED TYPE
Fig. 7 Example of Application Circuit
R3
C5
C2
UP(1)
VP1(3)
D2 ⁺
VUFB(4)
VUFS(6)
C1 D1 C2
R3
C5
C2
VP(7)
VP1(9)
D2 ⁺
VVFB(10)
VVFS(12)
C1 D1 C2
R3
C5
C2
WP(13)
VP1(14)
VPC(15)
VWFB(16)
D2 ⁺
VWFS(18)
C1 D1 C2
R3
UN(27)
C5
R3
VN(28)
C5
R3
WN(29)
C5
5V
CFO(25)
R2
Fo(26)
VOT(23)
HVIC
HVIC
HVIC
LVIC
IGBT1
Di1
IGBT2
Di2
IGBT3
Di3
IGBT4
Di4
IGBT5
Di5
IGBT6
Di6
P(40)
U(39)
V(38)
M
W(37)
+
C3
NU(36)
NV(35)
15V
VD
C1 ⁺ D1 C2
VN1(21)
VNC(22)
NW(34)
C
CIN(24)
C4
B
R1
VSC(19)
D
Rs Sense
resistor _A
Note
Control GND wiring ^N1 Power GND wiring
1 :If control GND and power GND are patterned by common wiring, it may cause malfunction by fluctuation of power GND level. It is recommended to connect
control GND and power GND at only a N1 point at which NU, NV, NW are connected to power GND line.
2 :It is recommended to insert a Zener diode D1 (24V/1W) between each pair of control supply terminals to prevent surge destruction.
3 :To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally inserting a
0.1μ~0.22μF snubber capacitor C3 between the P-N1 terminals is recommended.
4 :R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type. The time constant R1C4
should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time might vary with the wiring pattern, so the enough
evaluation on the real system is recommended. If R1 is too small, it may leads to delay of protection. So R1 should be min. 10 times larger resistance than Rs.
(100 times is recommended.)
5 :To prevent erroneous operation, the wiring of A, B, C should be as short as possible.
6 :For sense resistor, the variation within 1%(including temperature characteristics), low inductance type is recommended. And the over 1/8W is recommended,
but it is necessary to evaluate in your real system finally.
7 :To prevent erroneous SC protection, the wiring from V_SC terminal to CIN filter should be divided at the point D that is close to the terminal of sense resistor.
And the wiring should be patterned as short as possible.
8 :All capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency characteristic electrolytic type, and
C2: 0.22μ~2.0μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.)
9 :Input drive is High-active type. There is a min. 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring of each input should be as
short as possible. And it is strongly recommended to insert RC filter (e.g. R3=100Ω and C5=1000pF) and confirm the input signal level to meet the turn-on
and turn-off threshold voltage. Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
10 :Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to 1mA. (IFO is estimated
roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V, 10kΩ (5kΩ or more) is recommended.)
11 :Error signal output width (tFo) can be set by the capacitor connected to CFO terminal. CFO(typ.) = tFo x (9.1 x 10^-6) (F)
12 :High voltage (VRRM =1200V or more) and fast recovery diode (trr=less than 100ns or less) should be used for D2 in the bootstrap circuit.
13 :If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause erroneous operation. To avoid such problem, voltage
ripple of control supply line should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
14 :For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase IGBT or other DIPIPM.
Publication Date : January 2012
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