M30800MC Datasheet, PDF (62/317 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Preliminary Specifications REV.D
Specifications in this manual are tentative
Interrupts
and
subject
to
change.
M16C/80
SINGLE-CHIP
Mitsubishi microcomputers
(100-pin version) group
16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I Flag)
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set
(= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag
is automatically cleared to 0 after a reset is cleared.
Interrupt Request Bit
This bit is set (= 1) by hardware when an interrupt request is generated. The bit is cleared to 0 by
hardware when the interrupt request is acknowledged and jump to the interrupt vector.
This bit can be cleared to 0 (but cannot be set to 1) in software.
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When
an interrupt request is generated, the interrupt priority level of this interrupt is compared with the
processor interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is
greater than the processor interrupt priority level (IPL). This means that you can disable any particu-
lar interrupt by setting its interrupt priority level to 0.
Table 1.9.4 shows how interrupt priority levels are set. Table 1.9.5 shows interrupt enable levels in
relation to the processor interrupt priority level (IPL).
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag)
=1
• Interrupt request bit
=1
• Interrupt priority level
> Processor interrupt priority level (IPL)
The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the proces-
sor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.
Table 1.9.4 Interrupt Priority Levels
Interrupt priority
Interrupt priority level
level select bit
Priority
order
b2
0
b1
0
b0
0
Level 0 (interrupt disabled)
0 0 1 Level 1
Low
0 1 0 _{Level 2}
0 1 1 _{Level 3}
1 0 0 Level 4
1 0 1 Level 5
1 1 0 Level 6
1 1 1 _{Level 7}
High
Table 1.9.5 IPL and Interrupt Enable Levels
Processor interrupt Enabled interrupt priority
priority level (IPL)
levels
IPL2 IPL1 IPL0
000
001
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
010
011
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
100
101
Interrupt levels 5 and above are enabled.
Interrupt levels 6 and above are enabled.
1 1 0 Interrupt levels 7 and above are enabled.
1 1 1 All maskable interrupts are disabled.
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