M30800MC Datasheet, PDF (215/317 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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M16C/80
SINGLE-CHIP
Mitsubishi microcomputers
(100-pin version) group
16-BIT CMOS MICROCOMPUTER
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25^oC, CM15 = “1” unless
otherwise specified)
Table 1.28.19. Memory expansion mode and microprocessor mode (no wait)
Symbol
td(BCLK-AD)
Pa rameter
Address output delay time
Measuring condition
Standard
Min. Max.
Unit
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
th(RD-AD)
Address output hold time (RD standard)
-3
ns
0
ns
th(WR-AD) Address output hold time (WR standard)
td(BCLK-CS) Chip select output delay time
(Note)
ns
18
ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
-3
ns
th(RD-CS)
Chip select output hold time (RD standard)
0
ns
th(WR-CS) Chip select output hold time (WR standard)
Figure 1.28.1 ^(Note)
ns
td(BCLK-ALE) ALE signal output delay time
18
ns
th(BCLK-ALE) ALE signal output hold time
–2
ns
td(BCLK-RD) RD signal output delay time
18
ns
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
-5
ns
18
ns
-3
ns
(Note)
ns
th(WR-DB)
tw(WR)
Data output hold time (WR standard)
WR signal width
(Note)
ns
(Note)
ns
Note: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 ⁹
f(BCLK)
– 20 _[ns]
th(WR – DB) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
th(WR – AD) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
th(WR – CS) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
tw(WR) =
10 ⁹
f(BCLK) X 2 ^{– 15} [ns]
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