M30800MC Datasheet, PDF (51/317 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Udnedveerlopment
Preliminary Specifications REV.D
Specifications in this manual are tentative
Power Saving
and
subject
to
change.
M16C/80
SINGLE-CHIP
Mitsubishi microcomputers
(100-pin version) group
16-BIT CMOS MICROCOMPUTER
Transition of stop mode, wait mode
All oscillators stopped
Stop mode
CM10=“1”
Interrupt
Reset
Medium-speed mode
(Divided-by-8 mode)
WAIT
instruction
Interrupt
CPU operation stopped
Wait mode
Interrupt
CM10=“1”
Note 1
High-speed/medium-
speed mode
WAIT
instruction
Interrupt
CPU operation stopped
Wait mode
All oscillators stopped
Stop mode
CM10=“1”
Interrupt
Note 3
Note 1
Note 2
WAIT
CPU operation stopped
Low-speed/low power
dissipation mode
Note 4
instruction
Interrupt
Wait mode
Normal mode
(Please see the following as transition of normal mode.)
Note 1: Switch clocks after oscillation of main clock is fully stable. After stop mode or when main clock oscillation is stopped,
transferred to the middle speed mode.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: The main ckock devision register is set to the division by 8 mode (MCD="0816").
Note 4: When shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (MCD="0816").
Transition of normal mode
Please change according to a direction of an arrow.
High-speed/medium-speed mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
BCLK :f(XIN)/8
CM07=“0” MCD=“0816”
Main clock is oscillating
Sub clock is stopped
MCD=“XX16”
Note 1, 3
High-speed mode
BCLK :f(XIN)
CM07=“0” MCD=“1216”
CM04=“0”
Main clock is oscillating
Sub clock is oscillating
CM04=“1”
MCD=“XX16”
Note 1, 3
High-speed mode
BCLK :f(XIN)
CM07=“0” MCD=“1216”
Medium-speed mode
(divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode)
BCLK :f(XIN)/division rate
CM07=“0” MCD=“XX16”
Note 4
CM04=“1”
Medium-speed mode
(divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode)
BCLK :f(XIN)/division rate
CM07=“0” MCD=“XX16”
Note 4
CM07=“0” Note 1
MCD=“XX16” Note 3
CM04=“1”
Low-speed/low power dissipation mode
Main clock is stopped
Sub clock is oscillating
Low power
dissipation mode
CM07=“1” Note 2
CM05=“1”
BCLK :f(XCIN)
CM05=“1”
CM07=“1”
CM05=“0” Note 4
Note 1: Switch clocks after oscillation of main clock is fully stable.
Note 2: Switch clocks after oscillation of sub clock is fully stable.
Note 3: Set the desired division to the main clock division register (MCD).
Note 4: When shifting to division by 8 mode, MCD is set to "0816".
Figure 1.8.7. Clock transition
CM07=“0 Note 1
MCD=“XX16” Note 3
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
BCLK :f(XCIN)
CM07=“1”
CM07=“1”
Note 2
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