M66850J Datasheet, PDF (5/15 Pages) Mitsubishi Electric Semiconductor – SRAM TYPE FIFO MEMORY

MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
SWITCHING CHARACTERISTICS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Symbol
tAC
tWFF
tREF
tPAF
tPAE
tOE
tOLZ
tOHZ
tRSF
Data Access Time
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Almost-Full Flag
Read Clock to Almost-Empty Flag
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Enable to Output in High-Z
Reset to Flag and Output Valid time
Parameter
Limits
Min. Typ. Max. ^Unit
3
15
ns
15
ns
15
ns
15
ns
15
ns
3
13
ns
0
ns
3
13
ns
25
ns
TIMING CONDITIONS (Ta=0 – 70˚C, Vcc=5V±10%, GND=0V)
Symbol
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tSKEW1
tSKEW2
Parameter
Clock Cycle Time
Clock Pulse Width HIGH
Clock Pulse Width LOW
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Skew time between Read Clock and Write Clock for Empty Flag and Full Flag
Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full
Flag
Limits
Unit
Min. Typ. Max.
25
ns
10
ns
10
ns
6
ns
1
ns
6
ns
1
ns
25
ns
25
ns
25
ns
10
ns
40
ns
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND – 3.0V
3ns
1.5V
1.5V
See Figure 4
5.0V
1.1kΩ
D.U.T.
680Ω
30pF
Figure 4. Output Load
Including Test board and scope capacitances.
5