M66850J Datasheet, PDF (12/15 Pages) Mitsubishi Electric Semiconductor – SRAM TYPE FIFO MEMORY

• Programmable Full Flag Timing
MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
WCLK
WEN1
WEN2
(If Applicable)
PAF
RCLK
REN1
REN2
tCLKH
tCLKL
(4)
tENS tENH
tENS tENH
tPAF
Full-(m+1) words in FIFO(1)
Full-m words
in FIFO(2)
tSKEW2⁽³⁾
tPAF
tENS tENH
NOTES :
1. PAF offset=m.
2. 64-m words in for M66850, 256-m words in for M66851,512-m words in for M66852, 1024-m words in for M66853.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle.
If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state
untill the next rising edge of WCLK.
4. If a write is performed on this rising edge of the write clock,there will be Full-(m-1) words in the FIFO when PAF goes LOW.
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