M66850J Datasheet, PDF (1/15 Pages) Mitsubishi Electric Semiconductor – SRAM TYPE FIFO MEMORY

MITSUBISHI <DIGITAL ASSP>
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
SRAM TYPE FIFO MEMORY
DESCRIPTION
M66850/851/852/853 are very high-speed and clock synchronous
FIFO(First-In,First-Out) memories fabricated by high-speed CMOS
technology.
These FIFOs are applicable for a data buffer as networks and
communications.
The write operation is controlled by a write clock pin(WCLK) and
two write enable pins(WEN1,WEN2).
Data present at the data input pins(D0-D8) is written into the
Synchronous FIFO on every rising write clock edge when the
device is enabled for writing.
The read operation is controlled by a read clock pin(RCLK) and
two read enable pins(REN1,REN2).
Data is read from the Synchronous FIFO on every rising read clock
edge when the device is enabled for reading. An output enable
pin(OE) controls the states of the data output pins(Q0-Q8).
MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty
flag EF and the full flag FF are fixed flags. The almost empty flag
PAE and the almost full flag PAF are programmable flags. The
programmable flag offset is initiated by the load pin(LD).
PIN CONFIGURATION (TOP VIEW)
D1 5
D0 6
PAF 7
PAE 8
GND 9
REN1 10
RCLK 11
REN2 12
OE ¹³
29 _RS
28 _WEN1
27 _WCLK
26 _WEN2/LD
25 VCC
24 Q8
23 Q7
22 Q6
21 Q5
Outline 32P0(M66850 – 853J)
FEATURES
• Memory configuration 64words x 9bits (M66850J/FP)
256words x 9bits (M66851J/FP)
512words x 9bits (M66852J/FP)
1024words x 9bits (M66853J/FP)
• Write and Read Clocks can be independent
• Advanced CMOS technology
• Programmable Almost-Empty and Almost-Full flags
• High-speed : 25ns cycle time
• Package Available :
32-pin Pastic Leaded Chip Carrier(PLCC)
32-pin Low profile Quad Flat Package(LQFP)
D1 1
D0 2
PAF 3
PAE 4
GND 5
REN1 6
RCLK 7
REN2 8
24 _WEN1
23 _WCLK
22 _WEN2/LD
21 _VCC
20 Q8
19 Q7
18 Q6
17 Q5
APPLICATION
• Data Buffer for networks communications.
Outline 32P6B(M66850 – 853FP)
BLOCK DIAGRAM
RS
WCLK
WEN1
WEN2
D0-D8
–
RESET
LOGIC
INPUT
REGISTER
OFFSET
REGISTER
LD
WRITE
CONTROL
WRITE
POINTER
MEMORY
ARRAY
READ
POINTER
READ
CONTROL
OUTPUT
REGISTER
RCLK
REN1
REN2
EF
OE
FLAG
LOGIC
PAE
PAF
FF
–
Q0-Q8
1