M5M4V64S30ATP-8A Datasheet, PDF (5/51 Pages) Mitsubishi Electric Semiconductor – 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TBST
MRS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS /RAS /CAS /WE BA0,1 A11
H
X
X
X
X
X
L
H
H
H
X
X
L
L
H
H
V
V
L
L
H
L
V
X
L
L
H
L
XX
L
H
L
L
V
X
L
H
L
L
V
X
L
H
L
H
V
X
L
H
L
H
V
X
L
L
L
H
X
X
L
L
L
H
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
X
X
L
L
L
L
L
L
A10 A0-9
X
X
X
X
V
V
L
X
H
X
L
V
H
V
L
V
H
V
X
X
X
X
X
X
X
X
X
X
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
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