M5M4V64S30ATP-8A Datasheet, PDF (15/51 Pages) Mitsubishi Electric Semiconductor – 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

SDRAM (Rev.1.3)
Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank
addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval be-
tween one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC, although
the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge
all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the
precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-9
A10
2 ACT command / tRCmin
ACT
ACT READ
tRRD
Xa
Xb Y
tRCD
Xa
Xb 0
tRCmin
tRAS
PRE
tRP
1
ACT
Xb
Xb
A11
Xa
Xb
Xb
BA0,1
00
01 00
01
DQ
Qa0 Qa1 Qa2 Qa3
READ
Precharge all
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The
start address is specified by A8-0(X8), A9-0(X4) and the address sequence of burst data is defined by the
Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be
hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after
READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
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