M66271FP Datasheet, PDF (4/21 Pages) Mitsubishi Electric Semiconductor – OPERATION PANEL CONTROLLER

MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
OUTLINE
M66271FP is graphic display only controller for displaying a dot
matrix type LCD. This IC has a built-in display data memory
(VRAM) which is equivalent to 320×240 dots LCD.
q Control register
When access the control register from MPU side, use IOCS,
LWR,RD,A<4:0> and D<7:0>. Refer to Table-1,when set control
type inputs.
Control registers are R1 – R8 for the normal mode function and
R9 – R11 for the exclusive register for the LCD module built-in
system.
q VRAM
When access VRAM from MPU side, use MCS,HWR,LWR,
RD,BHE, A<13:0> and D<15:0>. And enable to correspond to
both 8-bit and 16-bit MPU by using MPUSEL input. Refer to
Figure-1 and Table-2 – 6 for a form of VRAM and input setting
for 8/16-bit MPU.
q Cycle steal system
Cycle steal is interact method of transferring display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle of OSC.
Basic timing is two clocks of OSC,and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
Difference in VRAM between 8-bit and 16-bit MPU
(1) When accessing built-in VRAM by 8-bit MPU
(MPUSEL="L",BHE="H",HWR="H" :set)
A<13:0>
MCS
LWR
D<7:0>
A<13:0>
CEC
WEC
VRAM
9600byte
DI<7:0>
DO<7:0>
RD
In accessing VRAM from MPU,output WAIT. Change WAIT to
"L" at the timing of the falling edge of overlapping with MCS and
(RD or LWR/HWR). And return to "H" at synchronizing with
rising edge of MPUCLK after internal processing.
Cycle steal system can transfer data with more efficient. This
function access with the cycle steal method as taking WAIT for
MPU during the display term with necessity for the display data
transfer from built-in VRAM to LCD. On other side, don't output
WAIT for keeping throughput of MPU during horizontal
synchronous term with no necessity for the display data transfer
from VRAM to LCD side.
Refer to the following description of cycle steal.
q Output to LCD side
LCD display data UD<3:0> output synchronized with the rising
edge of CP output per 4bits.
LP output synchronized with the falling edge of OSC when finish
the transfer of display data for a line.
Enable to adjust the fittest value of the frame frequency
requested by the LCD PANEL side with adjusting pulse width by
LPW register.
FLM output, when finish the transfer of display data of 1st line.
M output is the LCD alternating signal which is signal for driving
LCD by alternating current.
M-cycle enable to set variably by M-cycle variable register in
line unit, and enable to utilize for preventting LCD from being
inferior.
(2) When accessing built-in VRAM by 16-bit MPU
(2-1) In case MPU use A<0> and BHE for byte access
(MPUSEL="H",HWR="H":set)
A<13:1>
A<0>
MCS
LWR
D<7:0>
A<13:1>
A<0>
CEC
WEC
VRAM
4800byte
(Lower byte)
DI<7:0>
DO<7:0>
(2-2) In case MPU use LWR and HWR for byte access
(MPUSEL="H",BHE="H",A<0>="H":set)
A<13:1>
A<13:1>
MCS
LWR
D<7:0>
CEC
WEC
DI<7:0>
DO<7:0>
VRAM
4800byte
(Lower byte)
BHE
D<15:8>
RD
A<13:1>
A<0>
VRAM
CEC
WEC
4800byte
(Upper byte)
DI<15:8>
DO<15:8>
Figure-1 Difference in VRAM between 8-bit and 16-bit MPU
HWR
D<15:8>
RD
A<13:1>
CEC
WEC
DI<15:8>
VRAM
4800byte
(Upper byte)
DO<15:8>