M5M4V64S30ATP-8 Datasheet, PDF (28/48 Pages) Mitsubishi Electric Semiconductor – 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
Symbol Parameter
-8
-10
-12
Unit note
Min. Max. Min. Max. Min. Max.
CL=2 12
15
15
ns
tCLK CLK cycle time
CL=3 8
10
12
ns
tCH CLK High pulse width
3
4
4
ns
tCL CLK Low pulse width
3
4
4
ns
tT Transition time of CLK
1
10
1
10
1
10 ns
tIS Input Setup time (all inputs)
2
3
3
ns
tIH Input Hold time (all inputs)
1
1
1
ns
tRC Row Cycle time
80
90
100
ns
tRCD Row to Column Delay
24
30
30
ns
tRAS Row Active time
56 10000 60 10000 70 10000 ns
tRP Row Precharge time
24
30
30
ns
tWR Write Recovery time
10
10
12
ns
tRRD Act to Act Delay time
16
20
24
ns 1
tCCD Col to Col Delay time
8
10
12
ns
Mode Register Set
tRSC
Cycle time
16
20
24
ns
tSRX Self Refresh Exit time
8
10
12
ns
tREF Refresh Interval time
64
64
64 ms
Note:1 2 ACT commands are allowed within tRC.
CLK
Signal
1.4V
1.4V
Any AC timing is
referenced to the input
signal crossing through
1.4V.
MITSUBISHI ELECTRIC
28