M5M4V64S30ATP-8 Datasheet, PDF (26/48 Pages) Mitsubishi Electric Semiconductor – 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
Vdd
Supply Voltage
with respect to Vss
-0.5 ~ 4.6
V
VddQ Supply Voltage for Output with respect to VssQ
-0.5 ~ 4.6
V
VI
Input Voltage
with respect to Vss -0.5 ~ Vdd+0.5
V
VO
Output Voltage
with respect to VssQ -0.5 ~ VddQ+0.5 V
IO
Output Current
50
mA
Pd
Power Dissipation
Ta = 25 °C
1000
mW
Topr Operating Temperature
0 ~ 70
°C
Tstg
Storage Temperature
-65 ~ 150
°C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Parameter
Min.
Vdd
Supply Voltage
3.0
Vss
Supply Voltage
0
VddQ
Supply Voltage for Output
3.0
VssQ
Supply Voltage for Output
0
VIH
High-Level Input Voltage all inputs
2.0
VIL
Low-Level Input Voltage all inputs
-0.3
Limits
Typ.
3.3
0
3.3
0
Unit
Max.
3.6
V
0
V
3.6
V
0
V
Vdd+0.3
V
0.8
V
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Parameter
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CLK pin
Input Capacitance, I/O pin
Test Condition Limits (max.) Unit
VI=Vss
5
pF
f=1MHz
5
pF
Vi=25mVrms
5
pF
7
pF
MITSUBISHI ELECTRIC
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