M5M4V64S30ATP-8 Datasheet, PDF (25/48 Pages) Mitsubishi Electric Semiconductor – 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S30ATP-8, -10, -12
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads.
During writes, DQM masks input data word by word. DQM to write mask latency is 0.
During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2.
CLK
Command
DQM
Write
DQM Function
READ
DQ
D0
D2 D3
masked by DQM=H
Q0 Q1
Q3
disabled by DQM=H
25
MITSUBISHI ELECTRIC