MH28S72PJG-5 Datasheet, PDF (22/57 Pages) Mitsubishi Electric Semiconductor – 9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
CLK
/CS
/RAS
/CAS
WRITE CYCLE (dual bank)
BL=4,Latch mode(REGE="H")
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
tRRD
tRCD
tRC
tRAS
tRRD
tRP
tRCD
/WE
CKE
DQM
tWR
tWR
A0-9
X
XY
Y
X
XY
A10
A11
X
X
X
X
X
X
X
X
BA0,1
0
10
10
01 2 0
REGE
DQ
D0 D0 D0 D0 D1 D1 D1 D1
D0 D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001 22