MH28S72PJG-5 Datasheet, PDF (18/57 Pages) Mitsubishi Electric Semiconductor – 9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BUFFER MODE
Symbol Parameter
tAC ^{Access time from CK}
CL=2
-5
Min. Max.
5.4
Limits
-6
Min. Max.
6
-7
Min. Max.
Unit
6 ^ns
CL=3
5.4
5.4
6 _ns
tOH
Output Hold time
from CK
tOLZ
Delay time, output low
impedance from CK
CL=2 3
3
3
ns
CL=3 ₃
3
3
ns
0
0
0
ns
Delay time, output high
tOHZ _{impedance from CK}
CL=2 _{3 5.4 3 6 3}
CL=3 3 5.4 3 5.4 3
6 ns
6 ns
Note)
1 If c lock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
V OUT
50pF
CK
DQ
1.4V
1.4V
Output Timing
Measurement
Ref erence Point
CK
DQ
tAC
tOH
tOHZ
1.4V
1.4V
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001 18