MH28S72PJG-5 Datasheet, PDF (1/57 Pages) Mitsubishi Electric Semiconductor – 9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH28S72PJG -5,-6,-7
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH28S72PJG is 134,217,728 - word x 72-bit
Sy nchronous DRAM stacked structural module. This
consist of t hirty -six industry standard 64M x 4
Sy nchronous DRAMs in TSOP.
The stacked structure of TSOP on a card edge dual in-
line package prov ides any application where high
densities and large of quantities memory are required.
This is a socket-ty pe memory m odule ,suitable f or
easy interchange or addition of m odule.
FEATURES
Frequency
CLK Access Time
(at Latch mode,Components)
-5
133MHz
5.4 n s(CL = 3 )
-6
133MHz
5.4 n s(CL = 4 )
-7
100MHz
6.0ns(CL=3)
Utilizes industry standard 64M X 4 Synchronous DRAMs in
TSOP package , industry standard Resister in TSSOP package ,
and industry standard PLL in TSSOP package.
Single 3.3V +/- 0.3V supply
Burst length 1/2/4/8/Full Page (programmable)
Burst type sequential / interleave (programmable)
Column access random
Burst W rite / Single W rite (programmable)
Auto precharge / Auto bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
8192 refresh cycles ev ery 64ms
APPLICATION
Main memory unit for computers, Microcomputer memory.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-406-0.2
MITSUBISHI
ELECTRIC
27/Mar. /2001 1