PS21562-P Datasheet, PDF (2/9 Pages) Mitsubishi Electric Semiconductor – AC100V~200V inverter drive for small power motor control.

MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21562-P
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
C1 : Tight tolerance, temp-compensated electrolytic type
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Inrush current
limiter circuit
High-side input (PWM)
(3, 5V line) (Note 1,2)
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter Level shifter Level shifter
Protection
circuit (UV)
Protection
circuit (UV)
Protection
circuit (UV)
Drive circuit Drive circuit Drive circuit
P
C2
(Note 8)
C1
(Note 6)
DIP-IPM
AC line input
H-side IGBTS
U
(Note 4)
V
M
W
C
Fig. 3
AC line output
Z
(Note 7)
N1
N
VNC
VNO
CIN
L-side IGBTS
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
Input signal conditioning
Fo logic
Drive circuit
Protection
circuit
Control supply
Under-Voltage
protection
Low-side input (PWM)
FO CFO
(3, 5V line) (Note 1, 2) _{Fault output (5V line)}
(Note 3, 5)
(Note 8)
VNC
VD
(15V line)
Note1:
2:
3:
4:
5:
6:
7:
8:
Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P-N1 DC power input pins.
Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
The terminal VNO should be connected to the terminal N outside of DIP-IPM.
To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) nearby each pair of supply terminals.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
P
Drive circuit
External protection circuit
H-side IGBTS
L-side IGBTS
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
U
Trip Level
V
W
N1
Shunt Resistor
AN
(Note 1)
CR
VNC
Drive circuit
CIN
B
Protection circuit
C
(Note 2)
0
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Collector current
waveform
2
tw (µs)
Sep. 2005