M306V5ME Datasheet, PDF (131/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

MITSUBISHI MICROCOMPUTERS
M306V5ME-XXXSP
M306V5EESP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
s Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is
specified, so that a START condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the clock generated by the master.
When this bit is “1,” the master is specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing
function (See note).
• At reset
Note: The START condition duplication prevention function disables the following: the START condi-
tion generation; bit counter reset, and SCL output with the generation. This bit is valid from
setting of BB flag to the completion of 1-byte transmittion/reception (occurrence of transmission/
reception interrupt request) <IICIRQ>.
I²Ci status register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S1
IIC1S1
Address
02E216
02EA16
When reset
0001000?2
0001000?2
Bit Symbol
Bit name
Function
LRB
Last receive bit
0 : Last bit = “0”
1 : Last bit = “1”
(See note 1)
RW
AD0
General call detecting 0 : No general call detected
flag (See note)
1 : General call detected (See note 1)
AAS
Slave address comparison 0 : Address mismatch
flag (See note)
1 : Address match
(See note 1)
AL
Arbitration lost detecting 0 : Not detected
flag (See note)
1 : Detected
(See note 1)
PIN
I²C-BUS interface i
0 : Interrupt request issued
interrupt request bit
1 : No interrupt request issued (See note 2)
BB
Bus busy flag
0 : Bus free
1 : Bus busy
(See note 1)
TRX
MST
Communication mode
specification bits
b7b6
0 0 : Slave receive mode
0 1 : Slave transmit mode
1 0 : Master receive mode
1 1 : Master transmit mode
Notes 1: These bits and flags can be read out, but cannot be written.
2: This bit can be written only “1.”
Fig. 2.11.40 I²Ci status register (i = 0, 1)
SCL
PIN
IICIRQ
Fig. 2.11.41 Interrupt request signal generation timing
Rev. 1.0
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