GP2010 Datasheet, PDF (9/24 Pages) Mitel Networks Corporation – GPS Receiver RF Front End

GP2010
Notes on Pin Descriptions
1). Both pins 4 & 6 (V_EE (OSC)) are connected internally. If the VCO regulator is used (V_CC = +5.00V nominal) then both pins
4 & 6 must be left floating, with either pin de-coupled to V_CC (OSC) with a 100nF capacitor. In this configuration, the dc output
level of the regulator can be monitored from V_EE (OSC), with respect to V_CC (OSC) - NOT 0V (V_EE/GND). For operation at
V_CC <+4.0V, the VCO regulator cannot be used, and both V_EE (OSC) pins must be shorted to V_EE (REG) (Pin 7) -
see Fig. 7.
2). The Digital Interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelihood
of undesirable digital signals interfering with the IF strip. (Note the maximum allowable Power Supply Differential in the
Electrical Characteristics - page 4).
3). The 35.42MHz Bandpass filter should have a bandwidth of approx 2.0MHz. Ideally, this should be a DW9255 SAW filter.
CONTROL SIGNALS
Power Down
TEST
L
Normal Operation
Normal Operation
H
Powered Down
Test
Stage 1
Output
175 MHz
Stage 2
Input
175 MHz
Stage 2
Output
35 MHz
Stage 3
Input
35 MHz
M1 - 4 = Matching
Networks, incorporating
Balun transformers
MM11
MM22
MM33
MM44
IF
Output
RF
INPUT
33
34 36
Cs
29 _Stage
1
Cp
37
40
SSttaaggee
22
41 43
44
1
Stage
33
11
ADC 13
12
PLL
LOOP C1
FILTER
R1
2
3
C2
PLL
SYNTHESISER
Power
Down
Power
Detect
14
15 19 24
18
17
9
8
OPClk LD REF 2 TEST PDn PRESET PREF
AAGGCCCCoonntrtrool ^l
21
22
CLK
SIGN
MAG
C1 = 470nF
C2 = 10nF
R1 = 270Ω
Cagc = 100nF
Cs = 5pF
Cp = 1.5pF
Cagc
Fig. 3 GP2010 test circuit
OPERATING NOTES
A typical application circuit is shown in figure 4 with the
GP2010 front-end interfaced to the GP2021 12 channel
correlator integrated circuit. The RF input has an unmatched
input impedance (see page 4). The RF input matching com-
ponents Cs and Cp should be mounted as close to the RF
input as possible: also the Vee(RF) tracks must be kept as
short as possible. A SAW may be used as a 175.42MHz filter,
but this can be replaced by a simpler coupled-tuned LC filter
if there is no critical out-of band jamming immunity require-
ment. The DC bias to mixer 1 is provided via inductors L1 and
L2, which may form part of the 175.42MHz filter. The output
of mixer 2 requires an external dc bias, achieved with inductors
L3 and L4, which also serve to tune out the input capacitance
of the DW9255 SAW filter. The output of the SAW is tuned with
inductor L5. The AGC capacitor (Cagc) determines the AGC
time-constant. The PLL loop filter components are selected to
give a PLL loop bandwidth of approx. 10kHz. The IF Output
is normally used for test-purposes only, but is available to the
user if required. Typically a low noise preamplifier (gain
>+15dB) is used, and may be located with a remote antenna.
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Further information is contained in the Quality Bro-
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