GP2010 Datasheet, PDF (7/24 Pages) Mitel Networks Corporation – GPS Receiver RF Front End

Pin No.
17
18
19
20
21
22
23
24
25
26, 32
27, 28,
30, 31
Signal Name
PDn
Input/Output
Input
TEST
Input
LD
Output
V_EE (DIG)
AGC-
Input
Output
AGC+
Output
V_CC (DIG)
REF 2
Input
Input
REF 1
Input
V_CC (RF)
Input
V_EE (RF)
Input
GP2010
Description
Power-Down control input.
A TTL compatible input, which when set to logic high, will
disable ALL of the GP2010 functions, except the power-on
reset block. Useful to reduce the total power consumption of
the GP2010. If this feature is not required, the pin should be
connected to 0V (V_EE/GND).
Test control input - Disable PLL.
A TTL compatible input, which when set to logic high, will
disable the on-chip PLL, by disconnecting the divided-down
VCO signal to the phase-detector. The VCO will free run at its
upper range of frequency operation. If this feature is not
required, the pin should be connected to 0V (V_EE/GND).
PLL Lock Detect output.
A TTL compatible output, which indicates if the PLL is phase-
locked to the PLL reference oscillator. Will become logic high
only when phase-lock is achieved.
Negative supply to the PLL and A to D converter.
AGC Capacitor output - inverse phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.
AGC Capacitor output - true phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.
Positive supply to the PLL and A to D converter.
10.000MHz PLL Reference signal input .
Input to which an externally generated 10.000MHz PLL
reference signal should be ac coupled, if an external PLL
reference frequency source (e.g TCXO) is used (see fig. 6).
If no external reference is used, this pin forms part of the on-
chip PLL reference oscillator, in conjunction with an external
10.000MHz crystal (see fig. 5).
PLL reference oscillator auxillary connection.
Used in conjunction with Pin 24 (REF 2) to allow a 10.000MHz
external crystal to provide the PLL reference signal if no
external PLL reference frequency source (e.g TCXO) is used.
This pin should NOT be connected if an external TCXO is
being used (see fig. 5).
Positive supply to the RF input and Stage 1 IF mixer.
Both pins 26 & 32 (V_CC (RF)) are connected internally, but
must both be connected to V_CC externally, to keep series
inductance to a minimum.
Negative supply to the RF input and Stage 1 IF mixer.
Pins 27, 28, 30 & 31 are all connected internally, but must ALL
be connected to 0V (V_EE/GND) externally, to keep series
inductance to a minimum.
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