GP2010 Datasheet, PDF (2/24 Pages) Mitel Networks Corporation – GPS Receiver RF Front End

GP2010
ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)
Max. Supply Voltage
7V
Max. RF Input
+15dBm
Max. voltage on any pin
V_CC/V_DD + 0.5V
except LD (pin 19) and PReset (pin 9), which are 5.5V
Min. voltage on any pin
Storage Temperature
V_EE - 0.5V
-65°C to +150°C
Operation Junction Temperature
-40°C to +150°C
10MHz Reference Input
1.5V pk -pk
ESD PROTECTION
The GP2010 device is static sensitive. The most
sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.
PRODUCT DESCRIPTION
The GP2010 receives the 1575.42MHz signal
transmitted by GPS satellites and converts it to a 4.309MHz
IF, using a triple down-conversion. The 4.309MHz IF is
sampled to produce a 2-bit digital output. If the GP2010 is
used in conjunction with the GP2021 correlator, then the
GP2021 provides a sampling clock of 5.714MHz. This converts
the IF to a 1.405MHz 2-bit digital output at TTL levels.
The GP2010 can operate from a single supply from
+3V (nominal) to +5V (nominal).
A block diagram of the circuit is shown in figure 2.
IF STRIP
The input signal to the GP2010 is the GPS L1 signal
received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about
-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input compression
point of the GP2010 means that with subsequent IF filtering
it is possible to reject large out of band jamming signals, in
particular 900MHz as used by mobile telephones.The on-chip
PLL generates the first local-oscillator frequency at 1400MHz.
The output of the front-end mixer (Stage 1) at 175.42 MHz can
then be filtered before being applied to the second stage. The
double-balanced stage 1 mixer outputs are open-collectors,
and require external dc bias to V_CC.
The second stage contains further gain and a mixer
with a local oscillator signal at 140 MHz giving a second IF at
35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to V_CC.
The signal from stage 2 is passed through an external
filter with a 1dB bandwidth of 1.9MHz. The performance of this
filter is critical to system performance and it is recommended
that a SAW filter is used (part number DW9255, also available
from Mitel Semiconductor). The output of the filter then feeds
the main IF amplifier. This includes 2 AGC amplifiers and a
third mixer with a local oscillator signal at 31.111 MHz giving
a final IF at 4.309 MHz. There is an on-chip filter after the third
mixer which provides filtering centred on 4.309 MHz. The IF
output, which has 1kΩ output impedance, is provided for test
purposes. All of the signals within the IF amplifier are differential
including the filter inputs and outputs, except the IF output (pin
1), to reduce any common mode interference.
175.42MHz FILTER
(33,34)
(36,37)
35.42MHz FILTER
(40,41)
(43,44)
AGC CAPACITOR
(21)
(22)
(29)
RF Input
L1
(1575.42MHz)
FRONT
END
MIXER
1. 400GHz
2nd
STAGE
MIXER
140MHz
AGC
AGC
3rd
STAGE
MIXER
4.3MHz
FILTER
31.11MHz
(1)
IF Output
(4.309MHz)
VCO
(2)
EXTERNAL
LOOP
(3)
FILTER
VOLTAGE
REGULATOR
PLL
LOOP
FILTER
PLL LOCK ⁽¹⁹⁾
LOGIC O/P
(LD)
PLL REF I/P
(24)
10MHz (REF 2)
PHASE
DETECTOR
PLL
REFERENCE
OSCILLATOR
÷5
÷52
÷7
÷9
÷4
1.400GHz
PHASE-
LOCKED
LOOP
AGC
CONTROL
+1.21V
_
+
POWER-ON
RESET
POWER
CONTROL
REF 1 I/P
(FOR USE WITH
CRYSTAL REF
ONLY)
(25)
(14, 15)
40MHz CLOCK O/P
(FOR CORRELATOR
CHIP)
(OPCIK +/-)
(18)
(8)
BITE
(TEST)
POWER-ON
REFERENCE
I/P
(PREF)
(17)
POWER
DOWN I/P
(PDn)
(9)
POWER-ON
RESET O/P
(PRESET)
Fig. 2 Block diagram of GP2010
+Vr
-Vr
SIGN
O/P
LATCH
MAG
O/P
LATCH
A -> D
CONVERTER
(13)
SIGN
TTL O/P
(12)
MAG
TTL O/P
(11) SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)
2