VP5311C Datasheet, PDF (7/16 Pages) Zarlink Semiconductor Inc – NTSC/PAL Digital Video Encoder

REGISTER DETAILS
BAR
RA7-0
Base register
Register address.
PART ID 2-0
ID17-00
Part number
Chip part identification (ID) number.
REV ID
REV7-0
Revision number
Chip revision ID number.
GCR
YCDELAY
Global Control
Luma to Chroma delay.
High = 37ns luma delay, this may be
used to compensate for group delay in
external filters.
Low = normal operation (default).
RAMPEN
SLH&V
CVBSCLMP
Modulated ramp enable.
High = ramp output for differential phase
and gain measurements. A 27MHz clock
must be applied to PXCK pin.
Low = normal operation (default).
1 = Slave to HS and VS inputs
1 = Enables clamp on composite output,
to prevent flatenning of chroma peaks
and troughs.
VFS1-0
VOCR
CLAMPDIS
Video format select
VFS1 VFS0
0 0 NTSC (default)
0 1 PAL-B,D,G,H,I,N(Argentina)
1 0 PAL-M
1 1 Reserved
Video Output Control
High = Clamp signal disable
Low = normal operation with clamp signal
enabled (default).
CHRBW
Chroma bandwidth select.
High = ±1·3MHz.
Low = ±650kHz (default)
SYNCDIS
High = Sync disable (in composite video
signal). COMPSYNC is not affected.
Low = normal operation with sync
enabled (default).
BURDIS
High = Chroma burst disable.
Low = normal operation, with burst
enabled (default).
LUMDIS
High = Luma input disable - force black
level with synchronisation pulses main-
tained.
Low = normal operation, with Luma input
enabled (default).
CHRDIS
High = Chroma input disable - force
monochrome.
Low = normal operation, with Chroma
input enabled (default).
VP5311C/VP5511C
PEDEN
High = Pedestal (set-up) enable a
7·5 IRE pedestal on lines 23-262 and
286-525. Valid for NTSC/PAL-M only
HANC
LBW1-0
Horizontal Ancillary Data Control
Luma filter control
LBW1 LBW0
00
01
1X
-3dB Bandwidth
6.16MHz
4.34MHz
2.79MHz
DF2-0(read only) Digital Field Identification, 000=Field1
ANCTREN
Ancillary timing reference enable. When
High use FIELD COUNT from ancillary
data stream. When low, data is ignored.
ANCID
AN7-1
Parity
Ancillary data ID
Ancillary data ID
Parity bit (odd)
Only ancillary data in REC 656 data
stream with the same ID as this byte will
be decoded by the VP5311C/VP5511C to
produce H and V synchronisation and
FIELD COUNT.
SC_ADJ
SC7-0
Sub Carrier Adjust
Sub carrier frequency seed value, see
table 2.
FREQ2-0
FR17-00
Sub carrier frequency
24 bit Sub carrier frequency programmed
via I²C bus, see table 2. FREQ2 is the
most significant byte (MSB).
SCHPHM-L
SCH8-0
Sub carrier phase offset
9 bit Sub carrier phase relative to the
50% point of the leading edge of the
horizontal part of composite sync.
SCHPHM bit 0 is the MSB. The nominal
value is zero. This register is used to
compensate for delays external to the
VP5311C/VP5511C.
GPPCTL
CTL7-0
General purpose port control
Each bit controls port direction
Low = output High = input
GPPRD
RD7-0
General purpose port read data
I²C bus read from general purpose port
(only INPUTS defined in GPPCTL)
GPPWR
WR7-0
General purpose port write data
I²C bus write to general purpose port
(only OUTPUTS defined in GPPCTL)
CCREG1
F1W1D6-0
Closed Caption register 1
Field one (line 21), first data byte
CCREG2
F1W2D6-0
Closed Caption register 2
Field one (line 21), second data byte
CCREG3
F2W1D6-0
Closed Caption register 3
Field two (line 284), first data byte
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