VP5311C Datasheet, PDF (11/16 Pages) Zarlink Semiconductor Inc – NTSC/PAL Digital Video Encoder

VP5311C/VP5511C
PXCK Input (27MHz)
HS
Nck=1
Nck=0
t SU; PD
t HD; PD
Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3
Pixel Data Input (PD[7,0])
Fig.4 REC 656 interface with HS output timing
REFSQ
SC_SYNC
REFSQ
Divide by 4
Synchronous _Q
Counter
RESET
2:1 mux
0
1
f_SC
Input to
Genlocking
Block
FSC4_SEL
(register bit)
t PWH; SC_SYNC
t_{SU; SC_SYNC}
SC_SYNC
t HD; SC_SYNC
Q
Fig.5 REFSQ and SC_SYNC input timing
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