English
Language : 

VP5311C Datasheet, PDF (1/16 Pages) Zarlink Semiconductor Inc – NTSC/PAL Digital Video Encoder
Supersedes May 1997 edition DS4575 - 1.0
VP5311C/VP5511C
NTSC/PAL Digital Video Encoder
DS4773 - 2.3 March 1998
The VP5311C/VP5511C converts digital Y, Cr, Cb,
data into analog NTSC/PAL composite video and S-video
signals. The outputs are capable of driving doubly
terminated 75 ohm loads with standard video levels.
The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Cb, Y, Cr, Y
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311C/
VP5511C is working in slave mode.
The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.
All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.
The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.
Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.
FEATURES
s Converts Y, Cr, Cb data to analog composite video and
S-video
s Supports CCIR recommendations 601 and 656
s All digital video encoding
s Selectable master/slave mode for sync signals
s Switchable chrominance and luma bandwidth
s Switchable pedestal with gain compensation
s SMPTE 170M NTSC or CCIR 624 PAL compatible
outputs
s GENLOCK mode
s Line 21 Closed Caption encoding
s I2C bus serial microprocessor interface
s VP5311C supports Macrovision V7.01anti-taping format
APPLICATIONS
s Digital Cable TV
s Digital Satellite TV
s Multi-media
s Video games
s Karaoke
s Digital VCRs
ORDERING INFORMATION
VP5311C/CG/GP1N
VP5511C/CG/GP1N
PIN 52
PIN 1 IDENT
PIN 1
GP52
Fig.1 Pin connections (top view)
PIN FUNCTION
PIN FUNCTION
1
D0 (VS I/O)
27
RESET
2
D1 (HS I/O)
28
REFSQ
3
D2 (FC0 O/P)
29
GND
4
D3 (FC1 O/P)
30
PD7
5
D4 (FC2 O/P)
31
PD6
6
D5
32
PD5
7
D6 (SCSYNC I/P) 33
PD4
8
D7 (PALID I/P)
34
PD3
9
GND
35
PD2
10
VDD
36
PD1
11
GND
37
PD0
12
PXCK
38
GND
13
VDD
39
VDD
14
CLAMP
40
AGND
15
COMPSYNC
41
VREF
16
TDO
42
DACGAIN
17
TDI
43
COMP
18
TMS
44
AVDD
19
TCK
45
LUMAOUT
20
GND
46
AGND
21
SA1
47
COMPOUT
22
SA2
48
AGND
23
SCL
49
CHROMAOUT
24
VDD
50
AVDD
25
SDA
51
AVDD
26
VDD
52
AVDD