ACE9050 Datasheet, PDF (7/52 Pages) Mitel Networks Corporation – System Controller and Data Modem Advance Information

TIMING DIAGRAMS
ACE9050
NORMAL MODE PROCESSOR INTERFACE
Read Cycle
ECLK
t_ECLK
ADDR
CS
OEN
DATA
t_ADVCSL
t_CSLCLL
t_OELCLL
t_DAVCLL
t_CLLADI
t_CLLCSH
t_CLLOEH
t_CLLDAI
Fig.4 ACE9050 6303 Read cycle timing diagram
Timing Cycle Conditions
Input clock frequency, XIN = 8·064MHz. Worst case Timings: T_AMB = 240°C to 185°C, V_DD = 13·6V to 15·5V
Typical timings: T_AMB = 125°C, V_DD = 13·75V
Description
Symbol
Normal clock
Min.
Typ. Max.
Turbo clock
Min.
Typ.
Max.
Cycle time
Address valid to CS low
Chip Select set-up time
OEN set-up time
Data set-up time
Data hold time
OEN hold time
CS hold time
Address hold time
t_ECLK
t_ADVCSL
t_CSLCLL
t_OELCLL
t_DAVCLL
t_CLLDAI
t_CLLOEH
t_CLLCSH
t_CLLADI
992
2
4
9
2
940
972
985
445
485
492
495
240
35
35
0
0
0
1
4
0
9
24
45
9
7
18
42
7
Table 3 ACE9050 6303 Read cycle timing
496
4
9
480
490
245
248
1
4
24
45
18
42
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
7